The present invention relates to heterogeneous multi-core integrated circuits, and, more particularly, to a system and method for debugging heterogeneous multi-core integrated circuits.
Multi-core integrated circuits are integrated circuits with multiple processor cores. The multiple processor cores may execute the same or different functions in cohesion during operation. Certain multi-core integrated circuits include two or more processor cores with each processor core executing a different function. Such multi-core integrated circuits are known as heterogeneous multi-core integrated circuits. For example, a heterogeneous multi-core integrated circuit may include a first processor core that is a general purpose processor and a second processor core that is a digital signal processor (DSP).
Processor cores in a heterogeneous multi-core integrated circuit execute different tasks or software programs simultaneously. A debugging process is used to detect any malfunction or bugs in the processor cores or in the tasks/software programs. Debugging apparatuses are widely used for debugging multi-core integrated circuits. A debugging apparatus is designed to debug a specific kind of processor core. During debugging, the debugging apparatus is connected to debug ports of the multi-core integrated circuit. The debugging apparatus typically includes a combination of hardware, and/or software that tests the operation of a corresponding processor core. The debugging apparatus provides input data at the input debug port of the multi-core integrated circuit. Output debug data is generated at an output debug port and is received by the debugging apparatus. The output data is checked with the required specifications to detect bugs and faults within the processor cores or the tasks/software programs executed by the processor cores.
In the case of heterogeneous multi-core integrated circuits, multiple debugging apparatuses are required for testing the processor cores. Each debugging apparatus must be connected to a debug port of a corresponding one of the processor cores. The processor cores also need to be tested one at a time, which significantly increases debugging time. For testing multiple processor cores simultaneously, an individual debugging apparatus must be connected to each debug port, which increases the complexity and cost of the debugging system. Presently, heterogeneous multi-core integrated circuits allow only limited debug configurations for debugging the internal processor cores.
It would be advantageous to have a system and method for debugging a heterogeneous multi-core integrated circuit that eliminates the above mentioned shortcomings, and reduces the debugging time and cost. It further would be advantageous to have a system for debugging a heterogeneous multi-core integrated circuit that provides flexibility to use a debugging apparatus supporting a specific processor core or an integrated debugging apparatus supporting multiple processor cores.